The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating precise components at submicron levels. Along with the need for smaller components, there has been a growing demand for capacitors having increased capacitances and reduced feature widths.
With respect to dynamic memory devices, storage node capacitor cell plates must be sufficiently large to retain an adequate charge. This is particularly significant when taking device noise and parasitic effects into account. As density of semiconductor devices, such as DRAM arrays, has continued to increase with industry trends, the issue of maintaining storage node capacitance has grown in importance.
In light of the above demands, several techniques have been proposed to increase the capacitance of capacitors without effecting the cell area. These techniques have included utilizing trench and stacked capacitor structures, as well as new dielectric material having increased dielectric constants.
Another approach for increasing capacitance while reducing feature size known in the art is discussed in U.S. Pat. No. 5,208,479. The method involves employing roughened polycrystalline silicon ("polysilicon") film, such as Hemi-Spherical Grain ("HSG") polysilicon, as a capacitor storage node. Fundamentally, by relying on roughened polysilicon, a larger surface area is formed for the same planar area that is available for the capacitor.
Given the advantages of roughened polysilicon, a storage node of a cell capacitor is typically formed by initially providing a doped polysilicon layer of approximately 800.ANG.A. Subsequently, the surface of the doped polysilicon layer is cleaned. Once cleaned, a roughened polysilicon layer of approximately 600.ANG.A is deposited superjacent the doped polysilicon layer. Upon depositing, the roughened polysilicon layer is doped using a high temperature dopant drive technique. The drive technique in doping the roughened polysilicon layer relies on driving dopant from the previously doped polysilicon layer upwards into to the roughened polysilicon layer.
However, the approach of upwardly drive doping has several shortcomings. One particular failing is the lack of uniformity in doping the roughened polysilicon. Referring to FIG. 1, a storage node is illustrated employing a roughened polysilicon layer 30, such as HSG, having non-uniform doping characteristics. A semiconductor substrate 10 is shown comprising a silicon dioxide layer 20 superjacent a polysilicon layer 15. While polysilicon layer 15 is downwardly drive doped, the same dopant is utilized to upwardly drive dope roughened polysilicon layer 30. It is this approach that ultimately causes a series of malformed regions 35 in layer 15. Ultimately, regions 35 effect the reliability and performance of storage node.
Referring to FIG. 2, a completed cell capacitor utilizing HSG technology is depicted having two defect regions 35' and 35". The capacitor comprises top and bottom electrodes, 40 and 45, and a dielectric layer 50 comprising Barium Strontium Titanate ("BST"), Oxide-Nitride-Oxide ("ONO") or Oxide-NitrideOxide-Nitride ("ONON") for example. Upon completion of the capacitor, regions 35' and 35" are formed. Regions 35' and 35"" develop during the step of etching access areas to create contacts to both storage nodes of the intended capacitor. The formation of regions 35' and 35" can be primarily attributed to the roughness of the surface associated with layer 30, as well as the lack of uniformity in doping layer 30. The lack of uniformity in doping contributes to regions 35' and 35", in part because the etching rates vary depending on the dopant concentration. FIG. 3 illustrates this point in a graph showing Dopant Concentration versus Thickness characteristics as they relate to etching rates, C1 and C2.
As such, there is a need for a method for doping the top roughened polysilicon layer independently from the doping of a the bottom polysilicon layer. In this light, there is a demand for a method which enables more uniform doping of the top roughened polysilicon layer and bottom polysilicon layer.